module barrel_shifter_16bit (
  input         clk,
  input         rst_n,
  input  [15:0] data_in,
  input  [3:0]  shift_amt,
  input         shift_dir,  // 0=left, 1=right
  output [15:0] data_out
);

  reg [15:0] stage1, stage2, result;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
      result <= 16'b0;
    else
      result <= stage2;
  end

  assign data_out = result;
endmodule